1. Field of the Invention
The present invention relates, in general, to memory devices and, more particularly, to a memory device having an open bit line architecture and a method of repairing the memory device.
2. Description of the Related Art
In a memory device having an open bit line architecture, sense amplifiers are commonly disposed between sub-arrays. Each sense amplifier is connected to two bit lines. The bit lines are connected to memory cells included in different adjacent sub-arrays. Further, in the memory device having an open bit line architecture, an edge sub-array, that is, a sub-array that is positioned on the edge, or perimeter, of the array, has dummy bit lines that are interleaved with normal bit lines. Memory cells connected to the dummy bit lines do not store data during normal operation.
In the meantime, with ever-increasing integration and capacity requirements for memory devices, the size of memory chips tends to increase. The increase in the size of memory chips is a direct factor that results in a decrease in wafer yield. One of methods of improving wafer yield is repair technology under which redundant memory cells are provided in a memory device and cells that are determined to be defective are replaced with the redundant memory cells.
In a conventional memory device having an open bit line architecture shown in FIG. 1, a normal (non-edge) sub-array 50 positioned in a non-edge region includes redundant word lines RWL, and redundant memory cells connected to the redundant word lines. Further, if defective cells are present among the memory cells, the defective cells are replaced with the redundant memory cells using a method of cutting fuses in a repair control unit 70, etc.
However, in edge sub-arrays 30 and 40, redundant word lines and redundant memory cells are not provided. Therefore, if the redundant memory cells in the normal sub-array 50 are exhausted through replacement, no additional defective cells can be repaired. Accordingly, in the conventional memory device having an open bit line architecture of FIG. 1 repairability is limited.